Embodiments of the present invention relates to an iterative technique that estimates parasitic effects in an integrated circuit based on interconnect geometry estimations.
As is known in integrated circuit design, it is desirable to avoid transmission delays that may occur when transmitting data across interconnect within an integrated circuit (“IC”). “Interconnect” refers generally to data buses internal to an IC. Conventionally, delay has been dominated by transmitter and receiver circuitry at terminal ends of the interconnect. But more recently, transmission delays are being dominated by RC delay of the interconnect itself. Parasitic effects that are imposed upon the interconnect by other components of the IC are a major cause of RC delay. They are determined to a great degree by the topology of the interconnect and by the proximity of the interconnect to the other components. Parasitic effects can interfere with the propagation of data signals on the interconnect and, consequently, can cause timing requirements for such data signals to be missed. Accordingly, designers of ICs must account for these parasitic effects as they design the ICs.
Conventionally, designers have performed two calculations of parasitic effects during the design stage. A first parasitic calculation is an estimation that typically is performed very early in the circuit design stage when very little is known about the topology of the IC. Parasitic estimation at the early stage typically is based upon certain assumptions based on worst-case approximations of circuit topology and interconnect geometries. The early estimate produces very general parasitic estimations and typically were used only to confirm the feasibility of certain topologies and certain timing schemes.
A second parasitic calculation is a parasitic “extraction” that typically is performed very late in the circuit design stage when precise component layouts and interconnect geometries have been defined. This later parasitic estimation is much more accurate than the earlier estimation that is done before circuit layout occurs. The extraction actually calculates RC effects that will be imposed on every wire of the interconnect based upon that wire's neighbors. The later parasitic extraction determines whether the feasibility studies of the earlier parasitic estimation remain valid and whether the interconnect is likely to meet the timing requirements on which other components depend. In some cases, the extraction will reveal that the parasitic effects are likely to cause the interconnect (‘the net’) to fail its timing requirements. In this case, circuit designers must redesign the circuit or the interconnect geometry to find a design solution for which the parasitics pass the interconnect timing requirements.
Several tools are available to perform parasitic extraction. They include the Calibre and xCalibre products commercially available from Mentor Graphics Corporation of Wilsonville, Oreg. These extraction tools require the IC to be completely designed, both the interconnect and the other components, before extraction is possible.
The conventional two-stage parasitic estimation/extraction process is disadvantageous because it is based on a hit-or-miss approach; it does not converge iteratively on a valid circuit design. Typically, an early estimation is performed, then the results are shelved, possibly for several years, until the circuit design becomes sufficiently concrete for the extraction to be performed. Circuit designers can devote substantial resources building a circuit design based upon a favorable early parasitic estimation only to learn from a parasitic extraction that the IC design does not satisfy the IC's timing requirements. A circuit designer may be forced to undertake substantial resources in IC redesign under this method.
Accordingly, there is a need in the art for a parasitics estimation technique that is available for use throughout the circuit design process. There is a need for such an estimation technique that enables a design process that converges upon a design solution that meets timing requirements for internal interconnect within an IC.